Transmitting data through back-planes (routers) or optical systems is common for many data communications systems and networks. Due to limitations of various components in such systems, large pattern jitter is often introduced that causes distinct eye patterns to occur, most notably those with skewed and asymmetric jitter distributions (or histograms). Typical phase detectors, whether of the linear or non-linear type, do not lock the recovered clock to an ideal position within such an input data jitter distribution, thus reducing the effective total input jitter tolerance of a clock and data recovery circuit. In such cases, the use of typical phase detectors and CDR circuits can cause undesirable behavior, such as bit errors, even if the eye opening of the input data signal is wide enough to properly retime the input data using a decision circuit.